915GM Datasheet, PDF (17/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Errata
4.
Incorrect PCI Express Lane Transition after Receiving Several TS1
Packets
Problem:
If the GMCH receives several TS1 packets with Link and Lane numbers set to PAD,
after 4 µs it will time out and transition into configuration state instead of going
directly to the Detect state as it should. However, the link will still transition to the
Detect state after timing out of Configuration.
Implication: The GMCH will experience longer latency when transitioning to Detect state.
Workaround: None
Status:
For the steppings affected, see the Summary Tables of Changes.
5.
DMI Link Egress Port Address Is Not Programmable
Problem:
The PCI SIG approved ECR 04 to allow future system software (e.g., operating
system) to discover the link structure of the Root Complex. One of the registers in the
GMCH that “points” from the DMI port to the ICH cannot be programmed correctly.
Implication: There is no impact on platform functionality. ECR’s do not retroactively apply to the
current PCI Express* 1.0a Specification and no existing software understands the Root
Topology discovery structures. These structures are implemented in the GMCH only to
aid future software development. Such software will need to comprehend the incorrect
pointer
Workaround: None
Status:
For the steppings affected, see the Summary Tables of Changes.
6.
DDR2 OCD Nonfunctional
Problem:
During BIOS initialization the GMCH will not be able to adjust and set the DDR2-DRAM
Device DQ/DQS/DQS# buffer impedance.
Implication: Adjustable DQ/DQS/DQS# buffer impedance settings will not be programmed into the
DDR2-DRAM Devices, and the DRAM device OCD default output characteristics will be
used instead.
Workaround: None
Status:
For the steppings affected, see the Summary Tables of Changes.
7.
PCI Express* Graphics Initiated Snooped Reads to Memory That Are
Fast Dispatched Could Result in Incorrect Data Being Returned
Problem:
This has only occurred at 1.05-V Core and 533-MHz FSB. GMCH could provide
incorrect data for a PCI Express Graphics initiated memory read.
Implication: Could cause a data miscompare or system hang.
Workaround: It is possible for system BIOS to contain a workaround. Contact your Intel field
representative for more details.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
17