915GM Datasheet, PDF (40/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Bit
23:20
19
18
17
Access
and
Default
R/W
6h
RO
0b
R/W
0b
R/W
0b
Description
Activate to Precharge Delay (tRAS):
This bit controls the number of DRAM clocks for tRAS. Minimum
recommendations are beside their corresponding encodings.
0000: Reserved
0001: Reserved
0010: Reserved
0011: Reserved
0100: 4 clocks
0101: 5 clocks
0110: 6 clocks
0111: 7 clocks
(DDR333)
1000: 8 clocks
1001: 9 clocks
(DDR 2 400)
1010: 10 clocks
1011: 11 clocks
1100: 12 clocks
(DDR 2 533)
1101: 13 clocks
1110: 14 clocks
1111: 15 clocks
Recommended values:
7h DDR 333
9h DDR 2 400
Ch DDR 2 533
Reserved
Reserved
Activate to Activate Delay:
Control Act to Act delay between the different banks of the same rank.
Trr is specified in “ns”. 10 ns for 2-KB page size and 7.5 ns for 1-KB page
0 = 2 Clock
1 = 3 Clock
40
Specification Update