915GM Datasheet, PDF (38/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Bit
Access
and
Default
Description
9
R/W
Gate Core Display Clock (GCRC):
0b
0: Core display clock (cdclk) is running
1: Core display clock (cdclk) is gated
8
R/W
Asynchronously Change Core Display Clock (ACCDC):
0b
A 0 to 1 transition on this bit will immediately load new pre- and post-
divider values for the cdclk. Writing 1 to 1, 1 to 0, and 0 to 0 have no
effect.
7
R/W
Core Display Low Frequency Enable:
0b
0 = Do not Use low frequency target for Display Clock.
1 = Use low frequency target (152 MHz) for Display Clock. (For 915GMS only)
NOTE: This bit is reserved for 915GM / 915GME and 910GM / 910GMLE.
6:4
R/W
Graphics Core Display Clock Select:
000 b
000 = 190/200 MHz (Intel 915GM / 915GMS / 915GME and Intel 910GML /
910GMLE)
001 = 213/222 MHz (Intel 915GM / 915GME )
010 = Reserved
011 = Reserved
100 = 333 MHz (Intel 915GM/GME @ 1.5 V only)
101 = Reserved
110 = Reserved
111 = Reserved
3
RO
Reserved
0b
2:0
R/W
Graphics Core Render Clock Select:
000 b
000 = 160/166 MHz (Intel 915GM / 915GMS / 915GME and Intel 910GML /
910GMLE)
001 = 190/200 MHz (Intel 915GM / 915GME)
010 = Reserved
011 = Reserved
100 = 333 MHz (Intel 915GM/GME @ 1.5 V only)
101 = Reserved
Others = Reserved
38
Specification Update