915GM Datasheet, PDF (31/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Documentation Changes
1.
DRAM Enhanced Addressing Update
The following section is inserted into the Mobile Intel® 915 and 910 Express Chipset
Family of Products Datasheet Chapter 10, Section 10.2.1.3
10.2.1.3 DRAM Address Mapping
Enhanced Addressing swaps the most significant bit controlling one of the Sx_BS lines
with bit 18 (which normally controls row address bit 2). Without Enhanced Addressing,
rank bits are the most significant two bits of the address. With Enhanced Addressing,
the rank bits are always bits 19 and 20.
Table 10-8 DRAM Device Configurations – Dual Channel Asymmetric Mode
w/Enh. Addr. Swap (0)
Technology
(Mb)
Row bits
Column bits
Bank bits
Width (b)
Rows
Columns
Banks
Page Size (KB)
Devices per
rank
Rank Size
(MB)
Depth (M)
Addr bits [n:0]
Available in
DDR
Available in
DDRII
256
13
9
2
16
8192
512
4
4
4
128
16
26
yes
yes
256 512 512 512
13
10
2
8
8192
1024
4
8
13
10
2
16
8192
1024
4
8
13
11
2
8
8192
2048
4
16
13
10
2
16
8192
1024
4
8
8
4
8
4
256 256 512 256
32
32
64
32
27
27
28
27
yes yes yes
no
yes
no
no
yes
512
14
10
2
8
16384
1024
4
8
8
512
64
28
no
yes
1024
14
10
2
16
16384
1024
4
8
4
512
64
28
yes
no
1024
14
11
2
8
16384
2048
4
16
8
1024
128
29
yes
No
1024
13
10
3
16
8192
1024
8
8
4
512
64
28
no
yes
1024
14
10
3
8
16384
1024
8
8
8
1024
128
29
no
yes
Host Address
bit
Mem Addr-bit
31
-
-
-
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
r3
-
r3
29
-
-
-
r3
-
r3
r3
r 13
r3
r 13
Specification Update
31