915GM Datasheet, PDF (39/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
5.
Section 5.2.12 C0DRT1 – Channel 0 DRAM Timing Register 1
The following register bits definition replaces the Mobile Intel® 915 and 910 Express
Chipset Family of Products Datasheet; Section 5.2.12
Section 5.2.12 C0DRT1—Channel 0 DRAM Timing
Register 1
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
114h
00006111h
RO, R/W
32 bits
Bit
31:30
29:28
27:24
Access
and
Default
RO
00 b
R/W
00 b
R/W
0h
Description
Reserved
Read to Pre-charge (tRTPC):
These bits control the number of clocks that are inserted between a read
command to a row pre-charge command to the same rank.
Encoding tRP
00:
BL/2
01:
Reserved
10:
Reserved
11:
Reserved
Reserved
Specification Update
39