915GM Datasheet, PDF (16/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Errata
Errata
1.
Reported L0s Exit Latency Is Not Updated When PCI Express* Is Not
Operating in Common Clock Mode
Problem:
When PCI Express is operating with separate reference clocks, L0s exit latency may be
greater than the setting in the L0s Exit Latency register.
Implication: If the PCI Express link is operating in non-common clock mode, the actual L0s exit
latency may be longer than advertised. In this situation the link will likely enter the
Recovery state before transitioning into the normal L0 state.
Workaround: System BIOS can program the appropriate Exit Latency and advertised N_FTS value if
it detects that the downstream device is not using the common reference clock
(indicated in the Slot Clock Configuration bit 12 of the device’s Link Status register).
Status:
For the steppings affected, see the Summary Tables of Changes.
2.
GMCH Will Not Identify Back-to-Back Malformed Packets
Problem:
If the GMCH receives two back-to-back malformed packets, the second malformed
packet is not trapped or logged.
Implication: The GMCH will not log or identify the second malformed packet. However, the 1^st
malformed TLP is logged, and is considered a Fatal Error. Link behavior is not
guaranteed at that point whether a 2^nd malformed TLP is detected or not.
Workaround: None
Status:
For the steppings affected, see the Summary Tables of Changes.
3.
The GMCH Is Limited to Reporting Poisoned TLPs through Standard
PCI Error Status Reporting Structures
Problem:
The GMCH does not set the Non-Fatal Error Detected status bit, in the PCI Express
Device Status register when a poisoned TLP is received.
Implication: Future OS’s (that comprehend PCI Express error reporting) will not be notified via
standard PCI Express mechanisms when a poisoned TLP is received.
Workaround: Standard PCI error status reporting must be used for Poisoned TLP reporting. The
reception of Poisoned TLP is reported by hardware setting the Detected Parity Error bit
in Device 1, secondary status register, and if so enabled by additionally setting the
Master Data Parity Error bit in the same register.
Status:
For the steppings affected, see the Summary Tables of Changes.
16
Specification Update