915GM Datasheet, PDF (36/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
3.
Section 5.2.31 DCC – DRAM Channel Control
The following register bits definition replaces the Mobile Intel® 915 and 910 Express
Chipset Family of Products Datasheet; Section 5.2.31
Section 5.2.31 DCC—DRAM Channel Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
200h
00000000h
RO, R/W
32 bits
This register controls how the DRAM channels work together. It affects how the
CxDRB registers are interpreted and allows them to steer transactions to the correct
channel.
Bit
Access
and
Default
Description
10
R/W
Channel XOR Randomization Disable (CXRDIS): When enabled, the
DRAM Controller will try to spread page accesses evenly among the
0b
channels by including more address bits in the choice for which channel
holds the requested address.
0: Channel XOR Randomization is enabled. CXRSEL’s bit will be
XORed with CHSEL’s bit to pick the channel for a given address.
1: Channel XOR Randomization is disabled
9
R/W
Channel XOR Randomization Control Bit (CXRSEL): When Channel
XOR Randomization is in use (see CXRDIS), the channel select will be
0b
randomized by XORing it with either host address bit 11 or 17.
0: Bit 11 will be XORed with the Channel Select bit
1: Bit 17 will be XORed with the Channel Select bit
36
Specification Update