915GM Datasheet, PDF (46/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Access
Bit
&
Default
Description
Burst Length (BL):
The burst length is the number of QWORDS returned by a SO-DIMM per read
2
R/W
command, when not interrupted. This bit is used to select the DRAM
controller’s Burst Length operation mode. It must be set to match to the
0b
behavior of the SO-DIMM.
0: Burst Length of 4
1: Burst Length of 8
DRAM Type (DT):
Used to select between supported SDRAM types.
RO
00:
Reserved
1:0
01 b
01:
Dual Data Rate (DDR) SDRAM
10:
Dual Data Rate 2 (DDR 2) SDRAM
11:
Reserved
8.
Section 17.2.15 C0DRC1 – Channel 0 DRAM Controller Mode 1
The following register bit definition replaces the Mobile Intel® 915PM/GM/GME/GMS
and 910GML/GMLE Express Chipset EDS Volume 2.0 (Doc #17139); Section 17.2.15.
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
124h
00000000h
RO, R/W
32 bits
Bit
31
30
29:28
27
Access
&
Default
R/W
0b
R/W
0b
R/W
00 b
RO
0b
Reserved
Reserved
Reserved
Reserved
Description
46
Specification Update