915GM Datasheet, PDF (48/48 Pages) Intel Corporation – 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset

Documentation Changes
Bit
Access
&
Default
Description
DRAM Channel IO-Buffers Activate:
This bit is cleared to 0 during reset and remains inactive until it is set to 1
by BIOS. In addition, this bit can be cleared and set during debug
procedures.
R/W
While 0, the DRAM controller core logic forces the state of the IO-buffers
8
in this channel to “reset” or “preset”, depending on the specific buffer
0b
type. The buffers’ state flops (counters, pointers, etc) are forced into
their initial state. The core logic receive FIFO read pointer is forced into
its initial state. Output signal groups are driven to their initial state (tri-
stated). Refer to the following tables for the specific state.
While 1, the DRAM controller core logic enables the DRAM IO-buffers in
this channel to operate normally.
R/W
Reserved
7
0b
R/W
Reserved
6
0b
RO
Reserved
5
0b
4
R/W
Reserved
RO
Reserved
3:2
00 b
R/W
Reserved
1
0b
R/W
Reserved
0
0b
§
48
Specification Update