HYB25L512160AC Datasheet, PDF (8/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Overview
1.2
Description
The HYB25L512160AC consists of two 256MBit high-speed CMOS, dynamic random-access memories each of
them containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM.
The HYB25L512160AC achieves high speed data transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to the system clock. Read and write accesses are burst-
oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or
full page) in a programmed sequence.
The device operation is fully synchronous: all inputs are registered at the positive edge of CLK.
The HYB25L512160AC is especially designed for mobile applications: it adds many features to save power, like
low operating voltages. Additionally, current consumption in self refresh mode can further be reduced by using the
programmable Partial Array Self Refresh (PASR) and Temperature Compensated Self Refresh (TCSR).
A conventional data-retaining power down (PD) mode is available as well as a non-data-retaining deep power
down (DPD) mode.
The HYB25L512160AC is housed in a 54-ball “chip-size” FBGA package. It is available in Commercial (0°C to
70°C) temperature range.
Table 3 Ordering Information
Type¹⁾
Commercial Temperature Range
HYB25L512160AC–7.5
Description
133 MHz 2 × 4 Banks × 4 Mbit × 16 LP-SDRAM
1) HYB: Designator for memory products (HYB: standard temp. range)
25L: 2.5V Mobile-RAM
512: 512 MBit density
160: 16 bit interface width
A: die revision
C : lead-containing product
Package
FBGA-54
Data Sheet
8
Rev. 1.3, 2004-04
10212003-BSPE-77OL