HYB25L512160AC Datasheet, PDF (13/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
• V_DD and V_DDQ are driven from a single power converter output
• V_DDQ is driven after or with V_DD such that V_DDQ < V_DD + 0.3 V
After all power supply voltages are stable, and the clock is stable, the Mobile-RAM requires a 200µs delay prior to
applying a command other than DESELECT or NOP. CKE and DQM must be held high throughout the entire
power-up sequence. Once the 200µs delay has been satisfied, the following command sequence shall be applied
(see Figure 4):
• a PRECHARGE ALL command;
• at least 8 AUTO REFRESH commands;
• two MODE REGISTER SET commands for the Mode Register and Extended Mode Register
Following these cycles, the Mobile-RAM is ready for normal operation.
3.2
Register Definition
3.2.1 Mode Register
The Mode Register is used to define the specific mode of operation of the Mobile-RAM. This definition includes
the selection of a burst length, a burst type, a CAS latency, and a write burst mode. The Mode Register is
programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses power.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 WB 0 0 CAS Latency BT Burst Length
Address Bus
Mode Register
A9 Write Burst Mode
0
Burst Write
1
Single Write
A3 Burst Type
0 Sequential
1 Interleave
A6 A5 A4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
2
3
Reserved
Burst Length
A2 A1 A0
Sequential Interleave
000
1
1
001
2
2
010
4
4
011
8
8
100
Reserved
1 0 1 Reserved
110
1 1 1 full page
Figure 5 Mode Register Definition
Address bits A0-A2 specify the burst length, A3 the burst type, A4-A6 the CAS latency, A9 the write burst mode,
while bits A7-A8 and A10-A12 shall be written to zero.
Data Sheet
13
Rev. 1.3, 2004-04
10212003-BSPE-77OL