HYB25L512160AC Datasheet, PDF (21/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

3.4.4 ACTIVE
CLK
CKE
CS
RAS
CAS
WE
A0-A12
BA0,BA1
(High)
RA
BA
= Don't Care
Figure 12
BA = Bank Address
RA = Row Address
ACTIVE Command
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Before any READ or WRITE commands can be
issued to a bank within the Mobile-RAM, a row in that
bank must be “opened” (activated). This is
accomplished via the ACTIVE command and
addresses A0 - A12, BA0 and BA1 (see Figure 12),
which decode and select both the bank and the row to
be activated. After opening a row (issuing an ACTIVE
command), a READ or WRITE command may be
issued to that row, subject to the t_RCD specification. A
subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged).
The minimum time interval between successive
ACTIVE commands to the same bank is defined by
t_RC. A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access
overhead. The minimum time interval between
successive ACTIVE commands to different banks is
defined by t_RRD.
CLK
Command ACT
NOP
ACT
NOP
NOP
RD/WR
NOP
A0-A12 ROW
ROW
COL
BA0, BA1 BA x
BA y
BA y
t_RRD
Figure 13 Bank Activate Timings
t_RCD
= Don't Care
Table 9 Timing Parameters for Mode Register Set Command
Parameter
Symbol
– 7.5
Unit Notes
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE bank A to ACTIVE bank B delay
min.
max.
t_RC
67
—
ns
1)
t_RCD
19
—
ns
1)
t_RRD
15
—
ns
1)
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period ; round up to next integer.
Data Sheet
21
Rev. 1.3, 2004-04
10212003-BSPE-77OL