HYB25L512160AC Datasheet, PDF (28/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
CLK
Command READ
Address
Ba A,
Col n
DQM
DQ
DQ
NOP
NOP
NOP
NOP
WRITE
Ba A,
Col b
NOP
NOP
CL=2
DO n
CL=3
DO n+1
DO n
High-Z
High-Z
DI b
DI b+1 DI b+2
DI b
DI b+1 DI b+2
Ba A, Col n (b) = bank A, column n (b)
= Don't Care
DO n = Data Out from column n; DI b = Data In to column b;
DQM is asserted HIGH to set DQs to High-Z state for 1 clock cycle prior to the WRITE command.
Figure 24 READ to WRITE Timing
3.4.5.5 READ to PRECHARGE
A READ burst may be followed by, or truncated with a PRECHARGE command to the same bank (provided that
Auto Precharge was not activated), as shown in Figure 25.
The PRECHARGE command should be issued x clock cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency for READ bursts minus 1. Following the PRECHARGE
command, a subsequent ACTIVE command to the same bank cannot be issued until t_RP is met. Please note that
part of the row precharge time is hidden during the access of the last data elements.
In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time (as
described above) provides the same operation that would result from the same READ burst with Auto Precharge
enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address
busses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command
is that it can be used to truncate bursts.
CLK
Command READ
Address
Ba A,
Col n
A10 _{Dis AP}
(AP)
DQ
NOP
NOP
CL=3
NOP
PRE
t_RP
NOP
NOP
Ba A
Pre All
AP
Pre Bank A
ACT
Ba A,
Row a
DO n
DO n+1 DO n+2 DO n+3
Ba A, Col n = bank A, column n; BA Am Row = bank A, row x
= Don't Care
DO n = Data Out from column n
Burst Length = 4 in the case shown.
CAS latency = 3 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n.
Figure 25 READ to PRECHARGE Timing
Data Sheet
28
Rev. 1.3, 2004-04
10212003-BSPE-77OL