HYB25L512160AC Datasheet, PDF (29/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

3.4.6 WRITE
CLK
CKE
CS
(High)
RAS
CAS
WE
A0-A8
A10
BA0,BA1
CA
Enable AP
AP
Disable AP
BA
= Don't Care
Figure 26
BA = Bank Address
CA = Column Address
AP = Auto Precharge
WRITE Command
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
WRITE bursts are initiated with a WRITE command,
as shown in Figure 26. Basic timings for the DQs are
shown in Figure 27; they apply to all write operations.
CLK
DQM
DQ
t_IS
t_IH
t_IS
t_IH
DI n
DI n+2
= Don't Care
Figure 27 Basic WRITE Timing Parameters for DQs
The starting column and bank addresses are provided with the WRITE command, and Auto Precharge is either
enabled or disabled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the
completion of the write burst. For the generic WRITE commands used in the following illustrations, Auto Precharge
is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored. Figure 28 and Figure 29 show a single WRITE burst for each supported CAS latency setting.
Data Sheet
29
Rev. 1.3, 2004-04
10212003-BSPE-77OL