HYB25L512160AC Datasheet, PDF (34/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
3.4.6.3 WRITE - DQM Operation
DQM may be used to mask write data: when asserted HIGH, input data will be masked and no write will be
performed. The generic timing parameters as listed in Table 11 also apply to this DQM operation. The write burst
in progress is not affected and will continue as programmed.
CLK
Command NOP
Address
DQM
DQ
WRITE
Ba A,
Col n
DI n
NOP
NOP
NOP
DI n+2
DI n+3
NOP
Ba A, Col n = Bank A, Column n
= Don't Care
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following
DI n, with the first element (DI n+1) being masked.
DQM write latency is 0 clock cycles.
Figure 35 WRITE Burst - DQM Operation
3.4.6.4 WRITE to READ
A WRITE burst may be followed by, or truncated with a READ command. The READ command can be performed
to the same or a different (active) bank. With the registration of the READ command, data inputs will be ignored
and no WRITE will be performed, as shown in Figure 36.
Please note that truncation of a WRITE burst by a subsequent READ or WRITE is only possible when both
commands are issued to the same chip of this stacked configuration.
CLK
Command WRITE
Address
Ba A,
Col n
NOP
NOP
READ
Ba A,
Col b
DQ DI n
DQ DI n
DI n+1
DI n+2
Write data
are ignored
DI n+1
DI n+2
NOP
NOP
NOP
NOP
CL=2
High-Z
DO b
CL=3
High-Z
DO b+1 DO b+2
DO b
DI b+1
Ba A, Col n (b) = bank A, column n (b)
DI n = Data In to column n; DO b = Data Out from column b;
= Don't Care
Burst Length = 4 in the case shown.
3 subsequent elements of Data In (Out) are provided in the programmed order following DI n (DO b).
DI n+3 is ignored due to READ command. No DQM masking required at this point.
Figure 36 WRITE to READ Timing
Data Sheet
34
Rev. 1.3, 2004-04
10212003-BSPE-77OL