HYB25L512160AC Datasheet, PDF (15/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
3.2.1.2 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 5.
3.2.1.3 CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability
of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock
edge n + m (for details please refer to the READ command description).
3.2.1.4 Write Burst Mode
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.
3.2.2 Extended Mode Register
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR) and the Temperature Compensated Self Refresh (TCSR). The Extended Mode Register is
programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored
information until it is programmed again or the device loses power. The Extended Mode Register must be loaded
when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation.
Violating either of these requirements result in unspecified operation.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 TCSR
PASR
Address Bus
Mode Register
A4 A3
00
01
10
TCSR
70°C
45°C
15°C
A2 A1 A0
PASR
000
all banks
001
1/2 array (BA1 = 0)
010
1/4 array (BA1 = BA0 = 0)
011
Reserved
100
Reserved
101
1/8 array
(BA1 = BA0 = RA12 = 0)
1
1
0
1/8 array
(BA1 = BA0 = RA12 = RA11 = 0)
111
Reserved
Figure 6 Extended Mode Register Definition
Address bits A0-A2 specify the Partial Array Self Refresh (PASR) and bits A3-A4 the Temperature Compensated
Self Refresh (TCSR), while bits A5-A12 shall be written to zero.
Data Sheet
15
Rev. 1.3, 2004-04
10212003-BSPE-77OL