HYB25L512160AC Datasheet, PDF (12/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
3
Functional Description
The 512 Mbit Mobile-RAM consists of two 256MBit high-speed CMOS, dynamic random-access memories each
of them containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM.
READ and WRITE accesses to the Mobile-RAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12
select the row). The address bits registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the Mobile-RAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command description and device operation.
3.1
Power On and Initialization
The Mobile-RAM must be powered up and initialized in a predefined manner (see Figure 4). Operational
procedures other than those specified may result in undefined operation.
VDD
VDDQ
CLK
CKE
Command
Address
A10
BA0,BA1
DQM
DQ ^High-Z
200µs
t_CK
t_RP
t_RFC
t_RFC
t_MRD
t_MRD
NOP
PRE
ARF
All
Banks
ARF
MRS
CODE
CODE
MRS
CODE
CODE
NAOCTP
NROAP
NROAP
BA0=L
BA1=L
BA0=L
BA1=H
NBOAP
Power-up:
VDD and CK stable
Load
Mode
Register
Load
Ext.
Mode
Register
= Don't Care
Figure 4 Power-Up Sequence and Mode Register Sets
No power sequencing is specified during power up or power down provided that one of the following two criteria
is met:
Data Sheet
12
Rev. 1.3, 2004-04
10212003-BSPE-77OL