HYB25L512160AC Datasheet, PDF (31/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
CLK
Command ACT
Address
Ba A,
Row n
A10 (AP)
Row
x
DQ
t_RCD
NOP
NOP
t_RAS
t_RC
WRITE NOP NOP
Ba A,
Col n
Dis
AP
NOP
DI n DI n+1 DI n+2 DI n+3
t_WR
NOP PRE NOP
Pre All
AP
Pre Bank A
t_RP
NOP ACT
Ba A,
Row b
Row
b
Ba A, Col n = bank A, column n
DI n = Data In to column n
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n.
= Don't Care
Figure 29 WRITE Burst (CAS Latency = 3)
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either
case, a continuous flow of input data can be maintained. A WRITE command can be issued on any positive edge
of clock following the previous WRITE command. The first data element from the new burst is applied after either
the last element of a completed burst (Figure 30) or the last desired data element of a longer burst which is being
truncated (Figure 31). The new WRITE command should be issued x cycles after the first WRITE command,
where x equals the number of desired data elements.
Please note that truncation of a WRITE burst by a subsequent READ or WRITE is only possible when both
commands are issued to the same chip of this stacked configuration.
CLK
Command NOP
Address
DQ
WRITE
Ba A,
Col n
DI n
NOP
DI n+1
NOP
DI n+2
NOP
DI n+3
WRITE
Ba A,
Col b
DI b
NOP
DI b+1
NOP
DI b+2
NOP
DI b+3
Ba A, Col n (b) = Bank A, Column n (b)
DI n (b) = Data In to column n (b)
Burst Length = 4 in the case shown.
3 subsequent elements of Data In are provided in the programmed order following DI n (b).
Figure 30 Consecutive WRITE Bursts
= Don't Care
Data Sheet
31
Rev. 1.3, 2004-04
10212003-BSPE-77OL