HYB25L512160AC Datasheet, PDF (22/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

3.4.5 READ
CLK
CKE
CS
RAS
CAS
WE
A0-A8
A10
BA0,BA1
(High)
CA
Enable AP
AP
Disable AP
BA
= Don't Care
Figure 14
BA = Bank Address
CA = Column Address
AP = Auto Precharge
READ Command
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Subsequent to programming the mode register with
CAS latency and burst length, READ bursts are
initiated with a READ command, as shown in
Figure 14. Basic timings for the DQs are shown in
figure Figure 15; they apply to all read operations and
therefore are omitted from all subsequent timing
diagrams.
In order to prevent bus contention on the DQs,
care must be taken that a READ issued to one
chip does not interfere with a READ or WRITE
being in progress in the other chip of this stacked
configuration.
CLK
DQM
DQ
t_DQZ
t_AC
t_AC
t_HZ
t_LZ
t_OH
t_OH
DO n
DO n+1
Figure 15 Basic READ Timing Parameters for DQs
= Don't Care
Data Sheet
22
Rev. 1.3, 2004-04
10212003-BSPE-77OL