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HYB25L512160AC Datasheet, PDF (23/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM
HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
Table 10 Timing Parameters for READ
Parameter
Symbol – 7.5
Unit Notes
Access time from CLK
VDDQ = 2.3V .. 3.6V
VDDQ = 1.65V .. 1.95V
DQ low-impedance time from CLK
DQ high-impedance time from CLK
Data out hold time
DQM to DQ High-Z delay (READ Commands)
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command period
PRECHARGE command period
min. max.
tAC
—
tAC
—
6.0
ns 1)
8.0
ns 1)
tLZ
1.0
—
ns
tHZ
3.0
7.0
ns
tOH
3.0
—
ns
tDQZ
—
tRC
67
tRCD
19
tRAS
45
tRP
19
2
—
—
100k
—
tCK
ns 2)
ns 2)
ns 2)
ns 2)
1) tAC depends on VDDQ range; no dependency on CAS latency setting
2) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period ; round up to next integer.
The starting column and bank addresses are provided with the READ command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row being accessed starts precharge
at the completion of the burst, provided tRAS has been satisfied. For the generic READ commands used in the
following illustrations, Auto Precharge is disabled.
During READ bursts, the valid data-out element from the starting column address is available following the CAS
latency after the READ command. Each subsequent data-out element is valid nominally at the next positive clock
edge. Upon completion of a READ burst, assuming no other READ command has been initiated, the DQs go to
High-Z state.
Figure 16 and Figure 17 show single READ bursts for each supported CAS latency setting.
CLK
Command
Address
ACT
Ba A,
Row x
A10 (AP) Row x
DQ
tRCD
NOP
tRAS
tRC
READ
NOP
NOP
NOP
PRE
tRP
NOP
ACT
Ba A,
Col n
Dis AP
CL=2
Pre All
AP
Pre Bank A
Ba A,
Row b
Row b
DO n
DO n+1 DO n+2 DO n+3
Ba A, Col n = bank A, column n
AP = Auto Precharge
DO n = Data Out from column n
Dis AP = Disable Auto Precharge
Burst Length = 4 in the case shown.
3 subsequent elements of Data Out are provided in the programmed order following DO n.
Figure 16 Single READ Burst (CAS Latency = 2)
= Don't Care
Data Sheet
23
Rev. 1.3, 2004-04
10212003-BSPE-77OL