HYB25L512160AC Datasheet, PDF (40/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
CLK
t_RP
> t_RC
t_RC
t_RC
t_SREX
CKE
Command PRE
NOP
ARF
Address
A10 (AP) _{Pre All}
DQ
High-Z
NOP
NOP
NOP
ARF
NOP
ACT
Ba A,
Row n
Row n
Self Refresh
Self Refresh
Entry Command Exit Command
Figure 47 SELF REFRESH Entry and Exit
Exit from
Self Refresh
Any Command
(Auto Refresh
Recommended)
= Don't Care
Table 13 Timing Parameters for AUTO REFRESH and SELF REFRESH
Parameter
Symbol
– 7.5
Units
min.
max.
ACTIVE to ACTIVE command period
PRECHARGE command period
Refresh period (8192 rows)
Self refresh exit time
t_RC
67
t_RP
19
t_REF
—
t_SREX
1
—
ns
—
ns
64
ms
—
t_CK
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
Notes
1)
1)
1)
1)
3.4.10 POWER DOWN
CLK
CKE
CS
RAS
CAS
WE
A0-A12
BA0,BA1
= Don't Care
Figure 48 POWER DOWN Entry Command
Data Sheet
Power-down is entered when CKE is registered LOW
(no accesses can be in progress). If power-down
occurs when all banks are idle, this mode is referred to
as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred
to as active power-down. Entering power-down
deactivates the input and output buffers, excluding
CKE and CLK. In power-down mode, CKE LOW must
be maintained, and all other input signals are “Don’t
Care”. However, power-down duration is limited by the
refresh requirements of the device (t_REF).
The power-down state is synchronously exited when
CKE is registered HIGH (along with a NOP or
DESELECT command). One clock delay is required for
power down entry and exit.
Power-down entry and exit is common to both
stacked chips as they share a common CKE
signal.
40
Rev. 1.3, 2004-04
10212003-BSPE-77OL