HYB25L512160AC Datasheet, PDF (18/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
3.4
Commands
Table 6 Command Overview
Command
NOP DESELECT
NO OPERATION
CS RAS CAS WE DQM Address
HX X X X X
LH H H X X
Notes
1)
1)
ACT ACTIVE (Select bank and row)
LL
H HX
Bank / Row ²⁾
RD READ (Select bank and column and start read burst) L H L H L/H Bank / Col ³⁾
WR WRITE (Select bank and column and start write burst) L H L L L/H Bank / Col ³⁾
BST BURST TERMINATE or
LH H L X X
4)
DEEP POWER DOWN
PRE PRECHARGE (Deactivate row in bank or banks)
L L H L X Code
5)
ARF AUTO REFRESH or
LL L H X X
6)7)
SELF REFRESH (enter self refresh mode)
MRS
–
–
MODE REGISTER SET
Data Write / Output Enable
Write Mask / Output Disable (High-Z)
LL L L X
—— — — L
—— — — H
Op-Code ⁸⁾
—
9)
—
9)
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A12 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature
(nonpersistent), A10 LOW disables the Auto Precharge feature.
4) This command is BURST TERMINATE if CKE is HIGH; DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
5) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
6) This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
combinations of BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK. Figure 8 shows the basic timing parameters, which apply to all
commands and operations.
CLK
Input *)
t_CK
t_CH
Valid
t_IS t_IH
Valid
Figure 8
*) = A0 - A12, BA0, BA1, DQ0 - DQ15,
DQM, RAS, CAS, WE, CKE, CS
Address / Command Inputs Timing Parameters
t_CL
Valid
= Don't Care
Data Sheet
18
Rev. 1.3, 2004-04
10212003-BSPE-77OL