HYB25L512160AC Datasheet, PDF (47/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Electrical Characteristics
4.4
AC Characteristics
Table 20 AC Characteristics¹⁾
Parameter
Symbol
- 7.5
min. max.
Clock cycle time
V_DDQ = 2.3V .. 3.6V
CL = 3
t_CK
7.5
—
CL = 2
9.5
—
V_DDQ = 1.65V .. 1.95V CL = 2 or 3
9.5
Clock frequency
V_DDQ = 2.3V .. 3.6V
CL = 3
f_CK
—
V_DDQ = 1.65V .. 1.95V CL = 2 or 3
—
Access time from CLK V_DDQ = 2.3V .. 3.6V
CL = 2 or 3 t_AC
6.0
V_DDQ = 1.65V .. 1.95V
8.0
Clock high-level width
t_CH
2.5
Clock low-level width
t_CL
2.5
Address, data and command input setup time
t_IS
1.5
Address, data and command input hold time
t_IH
0.8
MODE REGISTER SET command period
t_MRD
2
DQ low-impedance time from CLK
t_LZ
1.0
DQ high-impedance time from CLK
t_HZ
3.0
Data out hold time
t_OH
3.0
DQM to DQ High-Z delay (READ Commands)
t_DQZ
—
DQM write mask latency
t_DQW
0
ACTIVE to ACTIVE command period
t_RC
67
ACTIVE to READ or WRITE delay
t_RCD
19
ACTIVE bank A to ACTIVE bank B delay
t_RRD
15
ACTIVE to PRECHARGE command period
t_RAS
45
WRITE recovery time
t_WR
14
PRECHARGE command period
t_RP
19
Refresh period (8192 rows)
t_REF
—
Self refresh exit time
t_SREX
1
—
133
105
—
—
—
—
—
—
—
—
7.0
—
2
—
—
—
—
100k
—
—
64
—
1) 0 °C ≤ T_C ≤ 70 °C (comm.); V_DD = 2.3V .. 3.6V; V_DDQ = 1.8 V ± 0.15 V; or 2.3V .. 3.6V;
All parameters assumes proper device initialization. AC timing tests measured at 0.9 V.
The transition time is measured between V_IH and V_IL; all AC characteristics assume t_T = 1 ns.
2) Specified t_AC and t_OH parameters are measured with a 30 pF capacitive load only as shown below:
I/O
30 pF
Unit Notes
ns —
ns —
ns —
MHz —
MHz
ns
2)3)
ns —
ns —
ns —
ns ⁴⁾
ns ⁴⁾
t_CK —
ns —
ns —
ns
2)5)
t_CK —
t_CK —
ns ⁵⁾
ns ⁵⁾
ns ⁵⁾
ns ⁵⁾
ns ⁶⁾
ns ⁵⁾
ms —
——
3) If t_T(CLK) > 1 ns, a value of (t_T/2 - 0.5) ns has to be added to this parameter.
4) If t_T > 1 ns, a value of (t_T - 1) ns has to be added to this parameter.
5) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
no. of clock cycles = specified delay / clock period; round up to next integer.
6) The write recovery time of t_WR = 14 ns allows the use of one clock cycle for the write recovery time when f_CK ≤ 72 MHz.
With f_CK > 72 MHz two clock cycles for t_WR are mandatory. Infineon Technologies recommends to use two clock cycles for
the write recovery time in all applications..
Data Sheet
47
Rev. 1.3, 2004-04
10212003-BSPE-77OL