HYB25L512160AC Datasheet, PDF (33/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

HYB25L512160AC–7.5
512MBit Mobile-RAM
Functional Description
CLK
Command NOP
WRITE
NOP
NOP
BST
Address
Ba A,
Col n
DQ
DI n
DI n+1
DI n+2
NOP
NOP
Ba A, Col n = Bank A, Column n
= Don't Care
DI n = Data In to column n
Burst Length = 4 in the case shown.
2 subsequent elements of Data In are written in the programmed order following DI n.
The burst is terminated after the 3rd data element.
Figure 33 Terminating a WRITE Burs
3.4.6.2 Clock Suspend Mode for WRITE Cycles
Clock suspend mode allows to extend any WRITE burst in progress by a variable number of clock cycles. As long
as CKE is registered LOW, the following internal clock pulse(s) will be ignored and no data will be captured, as
shown in Figure 34.
CLK
CKE
internal
clock
Command NOP
Address
DQ
WRITE
Ba A,
Col n
t_CSL
DI n
NOP
t_CSL
t_CSL
DI n+1
Ba A, Col n etc. = Bank A, Column n etc.
DO n etc. = Data Out from column n etc.
CL = 2 in the case shown
Clock suspend latency t_CSL is 1 clock cycle
Figure 34 Clock Suspend Mode for WRITE Bursts
NOP
NOP
DI n+2
= Don't Care
Data Sheet
33
Rev. 1.3, 2004-04
10212003-BSPE-77OL