HYB25L512160AC Datasheet, PDF (10/50 Pages) Infineon Technologies AG – 512MBit Mobile-RAM

2.1
Pin Description
HYB25L512160AC–7.5
512MBit Mobile-RAM
Pin Configuration
Table 4 Pin Description
Symbol Type Function
CLK Input Clock: all inputs are sampled on the positive edge of CLK.
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any
bank) or SUSPEND (access in progress). Input buffers, excluding CLK and CKE are disabled
during POWER-DOWN and SELF-REFRESH.
CS
(CS0,
CS1)
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for
external bank selection on systems with multiple memory banks. CS is considered part of the
command code
RAS,
CAS,
WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DQ0 - I/O
DQ15
Data Inputs/Output: Bi-directional data bus (16 bit)
DQM Input
(LDQM,
UDQM)
Input/Output Mask: input mask signal for WRITE cycles and output enable for READ
cycles. For WRITEs, DQM acts as a data mask when HIGH. For READs, DQM acts as an
output enable and places the output buffers in High-Z state when HIGH (two clocks latency) .
LDQM corresponds to DQ0 - DQ7, UDQM corresponds to DQ8 - DQ15.
BA0,
BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or
PRECHARGE command is being applied. BA0, BA1 also determine which mode register is
to be loaded during a MODE REGISTER SET command (MRS or EMRS).
A0 - A12 Input
Address Inputs: A0 - A12 define the row address during an ACTIVE command cycle. A0 -
A8 define the column address during a READ or WRITE command cycle. In addition, A10
(= AP) controls Auto Precharge operation at the end of the burst read or write cycle. During
a PRECHARGE command, A10 (= AP) in conjunction with BA0, BA1 controls which bank(s)
are to be precharged: if A10 is HIGH, all four banks will be precharged regardless of the state
of BA0 and BA1; if A10 is LOW, BA0, BA1 define the bank to be precharged. During MODE
REGISTER SET commands, the address inputs hold the op-code to be loaded.
V_DDQ
V_SSQ
V_DD
V_SS
Supply
Supply
Supply
Supply
I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity:
V_DDQ = 1.65V..1.95V; or 2.3V..3.6V
I/O Ground
Power Supply: Power for the core logic and input buffers. V_DD = 2.3V..3.6V
Ground
Data Sheet
10
Rev. 1.3, 2004-04
10212003-BSPE-77OL