MB81N643289 Datasheet, PDF (57/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
VDD
CAS
CS
TIMING DIAGRAM – 3 : OUTPUT CONTROL (1)
Entry
CAS must not brought from High to Low
DQ turn to Low-Z at CS=L and PD=H
DQ turn to High-Z at CS=H
PD
DQ0 to DQ31
DQS0 to DQS3
Memory device
output buffer status
This is not bus line level
High-Z
High-Z
tTLZ
Time (a)
Low-Z
Time (b)
tTHZ _High-Z
Time (c)
TIMING DIAGRAM – 4 : OUTPUT CONTROL (2)
VDD
CAS
CS
PD
Entry
CAS must not brought from High to Low
DQ turn to Low-Z at CS=L and PD=H
DQ turn to High-Z at PD=L
DQ0 to DQ31
DQS0 to DQS3
Memory device
output buffer status
High-Z
High-Z
tTLZ
Time (a)
Low-Z
Time (b)
tTHZ _High-Z
Time (c)
This is not bus line level
57