MB81N643289 Datasheet, PDF (29/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
(Continued)
Parameter
Symbol
Condition
Bust Read Current
(Average Power
Supply Current)
MB81N643289-50
MB81N643289-60
Bust Write Current
(Average Power
Supply Current)
MB81N643289-50
MB81N643289-60
Auto-refresh Current
(Average Power
Supply Current)
MB81N643289-50
MB81N643289-60
Self-refresh Current
(Average Power Supply Current)
IDD4R
IDD4W
IDD5
IDD6
Burst Length = 4,
CAS Latency = 3,
All bank active,
Gapples data,
tCK = min,
0 V < VIN < VIL (max),
VIH (min) < VIN < VDD
Burst Length = 4,
CAS Latency = 3,
All bank active,
Gapless data,
tCK = min,
0 V < VIN < VIL (max),
VIH (min) < VIN < VDD
Auto-refresh;
tCK = min, tREFC = min
0 V < VIN < VIL (max),
VIH (min) < VIN < VDD
Self-refresh;
PD = VIL,
0 V < VIN < VDD
Value
Unit
Min. Max.
510
—
mA
430
595
—
mA
505
320
—
mA
270
—
5 mA
Notes: *1. All voltages referenced to VSS.
*2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*3. IDD depends on the output termination or load conditions, clock cycle rate, and number of address and
command change within certain period. The specified values are obtained with the output open.
*4. Refer to output characteristics for the detail.
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