MB81N643289 Datasheet, PDF (24/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION (continued)
Fig. 3 – SDRAM READ TIMING EXAMPLE (@ CL=2 & BL=2)
<SDRAM >
t0
t1
t2
t3
t4
CLK
(external)
Command
DATA
RD
Stored by CLK input
Hi-Z
Q1
Q2
Output in every rising CLK edge
< DDR SDRAM >
t0
t0.5
t1
CLK
CLK
t1.5
t2
t2.5
t3
t3.5
t4
Command
DQS
DATA
RD
Stored by CLK input
Hi-Z
Low
Hi-Z
DQS signal tran-
sition occurs at
the same time as
data bus.
High
Q1
Q2
Output in every
cross point of clock input
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