MB81N643289 Datasheet, PDF (39/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Fig. 14 – AC TIMING, PULSE WIDTH
CLK
VX
VX
CLK
Input
(Controls &
Addresses)
Command
tRC, tRAS, tPCAL, tREF, tREFI, tREFC, tPAUSE
Command
Note: All parameters listed above are measured from the cross point at rising edge of the CLK and falling
edge of CLK of one command input to next command input.
PD
CLK
CLK
Fig. 15 – AC TIMING of Power Down Mode
tRC (min), tREF (max)
VREF
tPDE
lPDEX (min)
lPD
Command
NOP
PDEN
NOP
Don’t Care
PDEX
NOP
Note: Minimum 2 clock cycles is required for complete power down on clock buffer.
ACTV
Fig. 16 – AC TIMING of Self-refresh Mode
tREFC (min)^*2
PD
VREF
CLK
CLK
Command
tIS
NOP
Note *1
lPD
SELF
NOP
Don’t Care
tPDE
lLOCK (min)
NOP
NOP
ACTV
Note: 1. Minimum 2 clock cycles is required for complete power down on clock buffer.
2 PD must maintain High level and clock must be provided during the lLOCK period.
lLOCK must be satisfied before any command input.
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