MB81N643289 Datasheet, PDF (4/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s BLOCK DIAGRAM
Fig. 1 – MB81N643289 BLOCK DIAGRAM
CLK
CLK
PD
CS
RAS
CAS
WE
AC
A0 to A10
BA0,BA1,BA2
DM0 to DM3
DQ0
to
DQ31
DQS0 to
DQS3
4
CLOCK
BUFFER
Enable
To each block
...
COMMAND
DECODER
CONTROL
SIGNAL
LATCH
RAS
CAS
WE
Bank-7
...
Bank-1
Bank-0
MODE
REGISTER
DRAM
CORE
(2048 x 128 x 32)
ADDRESS
BUFFER/
REGISTER
I/O DATA
BUFFER/
REGISTER
&
DQS
GENERA-
TOR
VDDQ, VSSQ
11
...
ROW
ADDRESS
COLUMN
ADDRESS
COUNTER
COLUMN
7 ^ADDRESS
I/O
DLL
32
Clock Buffer
VDD
VREF
VSS / VSSQ