MB81N643289 Datasheet, PDF (16/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s STATE DIAGRAM
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second
*1
command
(same
bank)
First
command
MRS
lRSC
lRSC
lRSC
lRSC
lRSC
lRSC
ACTV
lRCD
*3
lRCD
lRCDW
*3
lRCDW
tRAS
tRAS
RD
lCCD
*3
lCCD
*2
lRWL
*2, 3
lRWL
*3
lRPL
*3
lRPL
RDA
*4, 5
lRDA
lRDA
*3
lRDA
*3
lRDA
*5
lRDA
*4, 5
lRDA
WR
lWRL
*3
lWRL
lCCD
*3
lCCD
*3
lWPL
*3
lWPL
WRA
PC
*5
lWAL
lWAL
*4, 5
tPCL
tPCL
*3
lWAL
*3
lWAL
*5
lWAL
*5
lWAL
*3
*5
*4, 5
1
1
tPCL
tPCL
PCA
*4
tPCAL
tPCAL
*4
1
1
tPCAL
tPCAL
REF
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
lLOCK
lLOCK
lLOCK
lLOCK
lLOCK
lLOCK
Notes: *1. Assume PCA command does not affect any operation on the other banks.
*2. Assume no I/O conflict.
*3. tRAS must be satisfied.
*4. Assume all outputs are in High-Z state.
*5. Assume all other banks are in idle state.
Illegal Command
16