MB81N643289 Datasheet, PDF (53/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge
command in POWER-UP INITIALIZATION. Once Precharge command is issued to SDRAM, it never get back to
SCITT Test Mode during regular operation for the purpose of a fail-safe way in get in and out of test mode.
1. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins and attempt to maintain all input
signals to be Low state (or at least PD to be Low state).
2. Apply VDD voltage to all VDDQ pins before or at the same time as VREF.
3. Apply VREF.
4. Maintain stable power for a minimum of 100µs.
5. Enter SCITT test mode.
6. Execute SCITT test.
7. Exit from SCITT mode.
It is required to follow Power On Sequence to execute read or write operation.
8. Start clock after all power supplies reached in a specified operating range and maintain stable condition
for a minimum of 200µs.
9. After the minimum of 200µs stable power and clock, apply NOP condition and take PD to be High state.
10.Issue Page Close All Banks (PCA) command or Page Close Single Bank (PC) command to every banks.
11.Issue EMRS to enable DLL, DE = Low.
12.Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lLOCK*¹
period is required to lock the DLL.
13.Apply minimum of two Auto-refresh command (REF).*²
14.Program the mode register by Mode Register Set command (MRS) with DR = Low.*²
The 5,6,7 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to POWER-
UP INITIALIZATION).
Notes: *1. The lLOCK depends on operating clock period. The lLOCK is counted from “DLL Reset” at step-8 to any
command input at step-10.
*2. The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
COMMAND TRUTH TABLE Note *1
Control
CAS CS PD
SCITT mode entry H→L *² L
L
SCITT mode exit L→H *³ H ^*5
L ^*5
SCITT mode
output enable *⁴
L
L
H
Input
Output
WE
RAS
A0 to A10,
BA0 to BA2
DM0
to
DM3
CLK,
CLK
DQ0
to
DQ31
DQS0
to
DQS3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
V
V
V
V
V
Notes: *1.
*2.
*3.
*4.
*5.
L = Logic Low, H = Logic High, V = Valid, X = either L or H
The SCITT mode entry command assumes the first CAS falling edge with CS and PD = L after power on.
The SCITT mode exit command assumes the first CAS rising edge after the test mode entry.
Refer the test code table.
CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
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