MB81N643289 Datasheet, PDF (47/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM – 13 : PAGE MODE READ / WRITE
(Timing assumes CL=3, BL=4, Same Bank Access)
CLK
CLK
lRCD
Command ACTV
NOP
RD
lRWL
NOP
WR
lWRL
NOP
RD
NOP
DQ
Hi-Z
Hi-Z
DQS
Q1 Q2 Q3 Q4
D1 D2 D3 D4
CL
WL
Notes: 1. lRWL : Letency of Read to Write command.
2. lWRL : Latency of Read to Write command in same bank.
TIMING DIAGRAM – 14 : PAGE MODE READ / WRITE
(Timing assumes CL=3, BL=4, Multiple Bank Access)
CLK
CLK
lRCD
Command ACTVa ACTVb NOP RDa
lRWL
NOP
WRb
lWRD
NOP
RDa
NOP
PCb PCa
Hi-Z
DQ
Hi-Z
DQS
Q1 Q2 Q3 Q4
D1 D2 D3 D4
Q1 Q2 Q3 Q4
CL (Bank a)
WL (Bank b)
CL (Bank a)
Notes: 1. lWRD : Latency of Write to Read command in different bank.
2. Data Strobe Input must be applied after or before output of DQS is in High-Z.
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