English
Language : 

MB81N643289 Datasheet, PDF (49/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM
MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM – 17 : SELF-REFRESH
(Timing assumes CL=2)
CLK
CLK
PD
tPDE
lLOCK
Command
NOP SELF NOP Don’t Care
SELFX
NOP
Any
Hi-Z
DQ
TIMING DIAGRAM – 18 : POWER DOWN
(Timing assumes any CL)
CLK
CLK
PD
Command
NOP PDEN
NOP
tPDE
lPDEX
PDEX NOP
Any
NOP
Hi-Z
DQ
Note: lPDEX : Latency of Power Down Exit to next command input delay.
tREF must be satisfied for burst refresh and tAREF must be satisfied for distributed
refresh.
49