MB81N643289 Datasheet, PDF (17/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s STATE DIAGRAM (continued)
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION
Second
command
(other
bank)
*7
*7
*7
*7
*8
*1, 8
First
*9
command
MRS
lRSC
lRSC
lRSC
lRSC
lRSC
lRSC
ACTV
*5
*10
*3, 10
*2, 10
*2, 10
lRRD
1
1
1
1
1
tRAS
RD
*5
*8
*2
*2, 8
1
lCBD
lCBD
lRWL
lRWL
1
*3
lRPL
RDA
*6
*5
*4
*3
*2
*2
lRDA
1
lCBD
lCBD
lRWL
lRWL
1
lRDA
*6
lRDA
*4, 6
lRDA
WR
*5
1
lWRD
*3
lWRD
lCBD
*3
lCBD
1
*3
lWPL
WRA
*6
*5
*3
*6
*6
lWAL
1
lWRD
lWRD
lCBD
lCBD
1
lWAL
lWAL
lWAL
*6
*5
*10
*3, 10
*2, 10
*2, 10
*3
*6
*4, 6
PC
tPCL
1
1
1
1
1
1
1
tPCL
tPCL
PCA
tPCAL
tPCAL
*4
1
1
tPCAL
tPCAL
REF
tREFC
tREFC
tREFC
tREFC
tREFC
tREFC
SELFX
lLOCK
lLOCK
lLOCK
lLOCK
lLOCK
lLOCK
Notes: *1. Assume PCA command does not affect any operation on the other bank(s).
*2. Assume no I/O conflict.
*3. tRAS must be satisfied.
*4. Assume all outputs are in High-Z state.
*5. Assume applicable bank is in idle state.
*6. Assume all other banks are in idle state.
*7. Assume the other bank(s) is in active state and lRCD or lRCDW is satisfied.
*8. Assume the other bank(s) is in active state and tRAS is satisfied.
*9. Second command have to follow the minimum clock latency or delay time of single bank operation in
other bank (second command is asserted.)
*10. Assume other banks are not in RD/RDA/WR/WRA state.
Illegal Command.
17