MB81N643289 Datasheet, PDF (42/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM – 3 : RANDOM WRITE
(Timing assumes CL=3, BL=4, Same Bank Access)
CLK
CLK
lRCDW
Command ACTV WR
lWPL
NOP
tPCL
PC NOP ACTV
NOP
DQ
Hi-Z
(Output)
DQS
Hi-Z
(Output)
WL (= CL-1)
D1 D2 D3 D4
tDQSS
Notes: 1 lRCDW : Letency of ACTV to Write command input delay is minimum 1 clock.
2 lWPL : Latency of Write command to Auto Close command lead time.
TIMING DIAGRAM – 4 : RANDOM WRITE WITH AUTO-CLOSE
(Timing assumes CL=3, BL=4, Same Bank Access)
CLK
CLK
lRCDW
lWAL
Command ACTV WRA
NOP
ACTV
NOP
DQ
Hi-Z
(Output)
DQS
Hi-Z
(Output)
WL (= CL-1)
D1 D2 D3 D4
tDQSS
Note: lWAL : Latency Write with Auto Close command to next Active command lead time.
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