MB81N643289 Datasheet, PDF (27/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s RECOMMENDED OPERATING CONDITIONS (Continued)
Notes:
VDD + 1V
VIH
Pulse width ≤ 4 ns
VIH
VIHmin
50% of pulse amplitude
VILmax
VIL
50% of pulse amplitude
VIL
Pulse width ≤ 4 ns
*1. Overshoot limit: VIH (max)
= VDD + 1V for pulse width <= 4 ns acceptable,
pulse width measured at 50% of pulse amplitude.
-1.0V
*2. Undershoot limit: VIL (min)
= VSS −1.0V for pulse width <= 4 ns acceptable,
pulse width measured at 50% of pulse amplitude.
*3. VREF is expected to track variations in the DC level of VDDQ of the transmitting device.
Peak-to-Peak noise level on VREF may not exceed +/- 2% of the supplied DC value.
*4. VISO means {VIN(CLK) + VIN(CLK)} / 2. Refer to Differential Input Signal Definition.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device.
All the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
Differential Input Signal Definition
Fig. 4 – Differential Input Signal Offset Voltage (For Clock Input)
CLK
CLK
VSS
|VSWING|
VX
VSWING(AC)
0V Differential
VISO
VSS
VISO (min.)
VISO (max.)
s CAPACITANCE
Parameter
Input Capacitance, Address & Control
Input Capacitance, CLK & CLK
Input Capacitance, DM0 to DM3
I/O Capacitance
Symbol
CIN1
CIN2
CIN3
CI/O
Min.
2.5
2.5
4.0
4.0
Typ.
—
—
—
—
(TA = 25°C, f = 1 MHz)
Max.
Unit
3.5
pF
3.5
pF
5.5
pF
5.5
pF
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