MB81N643289 Datasheet, PDF (44/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM – 7 : RANDOM READ
(Timing assumes CL=3, BL=4, Multiple Bank Access)
CLK
CLK
lRCD
lRDA
lRCD
Command ACTVa ACTVb NOP RDAa NOP RDAb NOP ACTVa ACTVb NOP RDAa
NOP
lRRD
lCBD
DQ
Hi-Z
(Output)
DQS
Hi-Z
(Output)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CL (Bank b)
CL (Bank a)
CL (Bank a)
Q1 Q2 Q3 Q4
Notes: 1 lCBD : Latency of CAS to CAS Bank Delay
2 lRRD : Latency of Active command to next Active command.
TIMING DIAGRAM – 8 : RANDOM READ
(Timing assume CL=3, BL=4, Multiple Bank Access)
CLK
CLK
lRCD
lRDA
tPCL
Command ACTVa ACTVb NOP RDa NOP RDb NOP RDa NOP RDb NOP PCa NOP ACVTa PCb
lRRD
DQ
Hi-Z
(Output)
DQS
Hi-Z
(Output)
lCBD
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CL (Bank a)
CL (Bank b)
CL (Bank a)
CL (Bank b)
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