MB81N643289 Datasheet, PDF (38/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Fig. 11 – AC TIMING of Read Mode (Clock to DQS Output Delay Time)
CLK
CLK
DQS Output
(@BL=4)
tQSLZ
(min)
Hi-Z
VIL
tCK
tCKQS
(min)
tQSPRE
tCK
tCKQS
(min)
tCKQS
(max)
tCKQS
(min)
tCKQS
(max)
tCKQS
(min)
tCKQS
(max)
VX
tQSHZ
tCKQS
(max)
tQSP
tQSP
tQSP
tQSPST
Note: DQS Access time (tQSCK) is measured from the cross point of clock (VX) and VREF.
The end of tQSPST and tQSHZ specification is defined at where output buffer is no longer driven.
CLK
CLK
DQ Data
Output
(@BL=4)
Fig. 12 – AC TIMING of Read Mode (Clock to Data Output Delay Time)
tCK
tCK
Hi-Z
tAC
(min)
tLZ
(min)
VIH
VIL
tAC
(min)
tAC
(max)
tAC
(min)
tAC
(max)
tAC
(min)
tAC
(max)
tOH
(min)
tAC
(max)
VX
tOH
(max)
tHZ
(max)
Note: Access time (tAC) is measured from the cross point of clock (VX) and VREF.
The end of tHZ specification is defined at where output buffer is no longer driven.
Fig. 13 – AC TIMING of Read Mode (DQS Output to Data Output Delay Time)
DQS Output
(@BL=4)
DQ Data
Hi-Z
Output
(@BL=4)
tQSQ
(min)
VIH
VIL
tQSQ
(min)
tQSQ
(max)
tQSQV
tQSQ
(min)
tQSQ
(max)
tQSQV
tQSQ
(min)
tQSQ
(max)
tQSQV
VREF
tQSQ
(max)
tQSQV
Note: DQS Output Edge to Data Output Edge Skew Time (tQSQ) is measured from VDDQ/2 to VDDQ/2.
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