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MB81N643289 Datasheet, PDF (56/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM
MB81N643289-50/-60 Preliminary (AE1E)
VCC
CAS
CS
TIMING DIAGRAM – 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence
and normal operation
Pause 100µs
tTS
tTH
Test Mode
tEPD
H→L
L
PD
L
*3
*2
Entry
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, PD pins will have some problems.
*2. PC or PCA commands must not be asserted. Test mode is disable by those commands.
*3. Outputs must be disabled by CS = H or PD = L before Exit.
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