MB81N643289 Datasheet, PDF (45/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
TIMING DIAGRAM – 9 : RANDOM WRITE
(Timing assumes CL=3, BL=4, Multiple Bank Access)
CLK
CLK
lWAL
Command ACTVa ACTVb NOP WRAa NOP WRAb
NOP
lRRD
DQ
Hi-Z
(Output)
DQS
Hi-Z
(Output)
lCBD
D1 D2 D3 D4 D1 D2 D3 D4
WL (Bank b)
WL (Bank a)
ACTVa ACTVb NOP NOP
TIMING DIAGRAM – 10 : RANDOM WRITE
(Timing assumes CL=2, BL=4, Multiple Bank Access)
CLK
CLK
lWPL
Command ACTVa ACTVb NOP WRa NOP WRb
NOP
tPCL
PCa NOP ACTVa PCb
lRRD
DQ
Hi-Z
(Output)
DQS
Hi-Z
(Output)
lCBD
D1 D2 D3 D4 D1 D2 D3 D4
WL (Bank b)
WL (Bank a)
NOP
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