MB81N643289 Datasheet, PDF (21/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s FUNCTIONAL DESCRIPTION (continued)
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access and MB81N643289 read and write operations are burst oriented.
The burst mode is implemented by keeping the same Row address and by automatic strobing Column address in
every single clock edge till programmed burst length(BL). Access time of burst mode is specified as tAC. The internal
column address counter operation is determined by a mode register which defines burst type(BT) and burst count
length(BL) of 2, 4 or 8 bits of boundary.
The burst type is sequential only. The sequential mode is an incremental decoding scheme within a boundary
address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end
of boundary address and then wraps round to the least significant address(= 0). If the first access of column address
is even (0), the next address will be odd (1), or vice-versa.
Burst Length
2
4
8
Starting Column Address
A2 A1 A0
XX0
XX1
X00
X01
X10
X11
000
001
010
011
100
101
110
111
Sequential Mode
0–1
1–0
0–1–2–3
1–2–3–0
2–3–0–1
3–0–1–2
0–1–2–3–4–5–6–7
1–2–3–4–5–6–7–0
2–3–4–5–6–7–0–1
3–4–5–6–7–0–1–2
4–5–6–7–0–1–2–3
5–6–7–0–1–2–3–4
6–7–0–1–2–3–4–5
7–0–1–2–3–4–5–6
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