MB81N643289 Datasheet, PDF (35/64 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT DOUBLE DATA RATE FCRAMTM

MB81N643289-50/-60 Preliminary (AE1E)
s AC CHARACTERISTICS (continued)
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure and stable
clock input with constant clock period and with 50% duty cycle.
*2. Access Times assume input slew rate of 1ns/volt between VREF+0.35V to VREF-0.35V, where VREF is
VDDQ/2, with 1 resistor and 1 capacitor load conditions. Refer to AC TEST LOAD CIRCUIT in page 36.
*3. VREF = 1.25V is a typical reference level for measuring timing of input signals.
Transition times are measured between VIH (min) and VIL (max) unless otherwise noted.
Refer to AC TEST CONDITIONS in page 36.
*4. This parameter is measured from the cross point of CLK and CLK input.
*5. This parameter is measured from signal transition point of DQS input crossing VREF level.
*6. tT is defined as the transition time between VIH (AC)(min) and VIL (AC)(max).
*7. All base values are measured from the cross point of the rising edge of CLK and falling edge of CLK
at the command input to the cross point of same clock input condition for the next command input.
All clock counts (= latency) are calculated by a simple formula:
clock count equals base value divided by clock period (round off to a whole number).
Clock >
Base Value
Clock Period
(Round off a whole number)
*8. Total of 4096 REF command must be issued within tREF(max). tREFC is a reference value for distributed
refresh and specifies the time between one REF command to next REF command except for a condition
where PD = L during Self-Refresh mode.
*9. Specified when the clock input is started on the condition of the stable supply voltage.
*10. Frequency dependent AC parameters are scalable by actual clock period (tCK) and affected by an abrupt
change of duty cycle, jitters on clock input, TA and level of VDD and VDDQ. The internal DLL circuit can
adjust delay time to change and following level change of VDD and VDDQ, (change rate of TA < 0.1 °C /
20 ns, change rate of VDD and VDDQ < 1 mV / 10 ns.
If change rate is bigger than these value, frequency dependent AC parameters affected by jitters causing
by these change.)
*11. More than 2 signal edge of DQS0-3 should not be input within 1 clock (tCK) cycle.
*12. Low-Z (Low Impecdnce State) is specified and measured at VDD / 2 +/- 200 mV from standby state.
*13. tHZ are specified where output buffer is no longer driven.
*14. Clock period must satisfy specified tCK and it must be stable.
Applicable also if device operating conditions such as supply voltages, case temperature, and/or clock
frequency (tCK difference must be 0.2 ns and under) is changed during any operation.
35