MC9S08GT16A Datasheet, PDF (95/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
6.5.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD)
Port E includes six general-purpose I/O pins that share with the SCI1 and SPI modules. Port E pins used
as general-purpose I/O pins are controlled by the port E data (PTED), data direction (PTEDD), pullup
enable (PTEPE), and slew rate control (PTESE) registers.
If the SCI1 takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SCI1 transmit pin, TxD1. PTEPE can be used, provided the corresponding
PTEDD bit is 0, to provide a pullup device on the SCI1 receive pin, RxD1.
If the SPI takes control of a port E pin, the corresponding PTEDD bit is ignored. PTESE can be used to
provide slew rate on the SPI serial output pin (MOSI or MISO) and serial clock pin (SPSCK) depending
on the SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit is 0, to provide
a pullup device on the SPI serial input pins (MOSI or MISO) and slave select pin (SS) depending on the
SPI operational mode.
Reads of PTED will return the logic value of the corresponding pin, provided PTEDD is 0.
7
R
0
W
Reset
0
6
5
4
3
2
0
PTED5
PTED4
PTED3
PTED2
0
0
0
0
0
Figure 6-24. Port E Data Register (PTED)
1
PTED1
0
0
PTED0
0
Table 6-17. PTED Field Descriptions
Field
Description
5:0
PTED[5:0]
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits in this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
95