MC9S08GT16A Datasheet, PDF (191/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (S08SPIV3)
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the shifter output is
routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the SPI, the shifter
output is routed to MISO, and the shifter input is routed from the MOSI pin.
In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all
MOSI pins together. Peripheral devices often use slightly different names for these pins.
PIN CONTROL
SPE
ENABLE
SPI SYSTEM
Tx BUFFER (WRITE SPID)
SHIFT
OUT
SPI SHIFT REGISTER
SHIFT
IN
M
MOSI
S
(MOMI)
M
MISO
S
(SISO)
LSBFE
Rx BUFFER (READ SPID)
SHIFT
DIRECTION
SHIFT Rx BUFFER Tx BUFFER
CLOCK
FULL
EMPTY
SPC0
BIDIROE
BUS RATE
CLOCK
SPIBR
CLOCK GENERATOR
MSTR
MASTER/SLAVE
MODE SELECT
CLOCK
LOGIC
MODE FAULT
DETECTION
MASTER CLOCK
SLAVE CLOCK
MODFEN
SSOE
M
S
MASTER/
SLAVE
SPSCK
SS
SPRF
SPTEF
SPTIE
MODF
SPIE
Figure 12-4. SPI Module Block Diagram
SPI
INTERRUPT
REQUEST
12.1.3 SPI Baud Rate Generation
As shown in Figure 12-5, the clock source for the SPI baud rate generator is the bus clock. The three
prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. The three rate
select bits (SPR2:SPR1:SPR0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256
to get the internal SPI master mode bit-rate clock.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
191