MC9S08GT16A Datasheet, PDF (202/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (S08SPIV3)
12.6.1.2 Pseudo—Code Example
In this example, the SPI module will be set up for master mode with only transmit interrupts enabled to
run at a maximum baud rate of bus clock divided by 2. Clock phase and polarity will be set for an
active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer.
SPIC1 = 0x74(%01110100)
Bit 7
SPIE
=0
Bit 6
SPE
=1
Bit 5
SPTIE
=1
Bit 4
MSTR
=1
Bit 3
CPOL
=0
Bit 2
CPHA
=1
Bit 1
SSOE
=0
Bit 0
LSBFE
=0
Disables receive and mode fault interrupts
Enables the SPI system
Enables SPI transmit interrupts
Sets the SPI module as a master SPI device
Configures SPI clock as active-high
First edge on SPSCK at start of first data transfer cycle
Determines SS pin function when mode fault enabled
SPI serial data transfers start with most significant bit
SPIC2 = 0x00(%00000000)
Bit 7:5
= 000
Bit 4
MODFEN = 0
Bit 3
BIDIROE = 0
Bit 2
=0
Bit 1
SPISWAI = 0
Bit 0
SPC0
=0
Unimplemented
Disables mode fault function
SPI data I/O pin acts as input
Unimplemented
SPI clocks operate in wait mode
SPI uses separate pins for data input and output
SPIBR = 0x00(%00000000)
Bit 7
=0
Bit 6:4
= 000
Bit 3
=0
Bit 2:0
= 000
Unimplemented
Sets prescale divisor to 1
Unimplemented
Sets baud rate divisor to 2
SPIS = 0x00(%00000000)
Bit 7
SPRF
=0
Bit 6
=0
Bit 5
SPTEF
=0
Bit 4
MODF
=0
Bit 3:0
=0
Flag is set when receive data buffer is full
Unimplemented
Flag is set when transmit data buffer is empty
Mode fault flag for master mode
Unimplemented
SPID = 0xxx
Holds data to be transmitted by transmit buffer and data received by receive buffer.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
202
Freescale Semiconductor