MC9S08GT16A Datasheet, PDF (91/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
6.5.3 Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD)
Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used
as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup
enable (PTCPE), and slew rate control (PTCSE) registers.
If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the SCI2 transmit pin, TxD2. PTCPE can be used, provided the corresponding
PTCDD bit is 0, to provide a pullup device on the SCI2 receive pin, RxD2.
If the IIC takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the IIC serial data pin (SDA), when in output mode and the IIC clock pin (SCL).
PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the IIC
serial data pin, when in receive mode.
Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0.
R
W
Reset
7
PTCD7
0
6
PTCD6
5
PTCD5
4
PTCD4
3
PTCD3
2
PTCD2
0
0
0
0
0
Figure 6-16. Port C Data Register (PTCD)
1
PTCD1
0
0
PTCD0
0
Table 6-9. PTCD Field Descriptions
Field
Description
7:0
PTCD[7:0]
Port C Data Register Bits— For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
91