MC9S08GT16A Datasheet, PDF (84/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Parallel Input/Output
6.2.5 Port E, SCI1, and SPI
Port E
Bit 7
6
5
4
3
2
1
Bit 0
MCU Pin: ⁰
0
PTE5/ PTE4/ PTE3/
SPSCK MOSI MISO
Figure 6-6. Port E Pin Names
PTE2/
SS
PTE1/
RxD1
PTE0/
TxD1
Port E is an 6-bit port shared with the SCI1 module, SPI1 module, and general-purpose I/O. When the SCI
or SPI modules are enabled, the pin direction will be controlled by the module function.
Port E pins are available as general-purpose I/O pins controlled by the port E data (PTED), data direction
(PTEDD), pullup enable (PTEPE), and slew rate control (PTESE) registers. Refer to Section 6.3, “Parallel
I/O Controls” for more information about general-purpose I/O control.
When the SCI1 module is enabled, PTE0 serves as the SCI1 module’s transmit pin (TxD1) and PTE1
serves as the receive pin (RxD1). Refer to Chapter 11, “Serial Communications Interface (S08SCIV1)” for
more information about using PTE0 and PTE1 as SCI pins.
When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as
the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5
serves as the SPI clock pin (SPSCK1). Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3) for
more information about using PTE5–PTE2 as SPI pins.
6.2.6 Port G, BKGD/MS, and Oscillator
Port G
Bit 7
MCU Pin: ⁰
6
5
4
3
0
0
0
PTG3
Figure 6-7. Port G Pin Names
2
PTG2/
EXTAL
1
Bit 0
PTG1/ PTG0/
XTAL BKGD/MS
Port G is an 4-bit port which is shared among the background/mode select function, oscillator, and
general-purpose I/O. When the background/mode select function or oscillator is enabled, the pin direction
will be controlled by the module function.
Port G pins are available as general-purpose I/O pins controlled by the port G data (PTGD), data direction
(PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers. Refer to Section 6.3, “Parallel
I/O Controls,” for more information about general-purpose I/O control.
The internal pullup for PTG0 is enabled when the background/mode select function is enabled, regardless
of the state of PTGPE0. During reset, the BKGD/MS pin functions as a mode select pin. After the MCU
exits reset, the BKGD/MS pin becomes the background communications input/output pin. The PTG0 can
be configured to be a general-purpose output pin. Refer to Section 5.7.4, “System Options Register
(SOPT),” for selecting BKGD or PTG0. Refer to Chapter 3, “Modes of Operation,”, Chapter 5, “Resets,
Interrupts, and System Configuration,” and Chapter 15, “Development Support,” for more information
about using this pin.
The ICG module can be configured to use PTG2–PTG1 ports as crystal oscillator or external clock pins.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
84
Freescale Semiconductor