MC9S08GT16A Datasheet, PDF (77/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

5.7.7
Resets, Interrupts, and System Configuration
System Power Management Status and Control 1 Register (SPMSC1)
7
6
5
4
3
2
1
0
R LVDF
W
0
LVDACK
LVDIE
LVDRE
Note ⁽¹⁾
LVDSE
Note ⁽¹⁾
LVDE
Note ⁽¹⁾
0
0
Reset
0
0
0
1
1
1
0
0
= Unimplemented or Reserved
1 _{This bit can be written only one time after reset. Additional writes are ignored.}
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-10. SPMSC1 Field Descriptions
Field
Description
7
LVDF
6
LVDACK
5
LVDIE
4
LVDRE
3
LVDSE
2
LVDE
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor
77