MC9S08GT16A Datasheet, PDF (194/300 Pages) Freescale Semiconductor, Inc – Microcontrollers

Serial Peripheral Interface (S08SPIV3)
Table 12-1. SPIC1 Field Descriptions (continued)
Field
4
MSTR
3
CPOL
2
CPHA
1
SSOE
0
LSBFE
Description
Master/Slave Mode Select
0 SPI module configured as a slave SPI device
1 SPI module configured as a master SPI device
Clock Polarity — This bit effectively places an inverter in series with the clock signal from a master SPI or to a
slave SPI device. Refer to Section 12.5.1, “SPI Clock Formats” for more details.
0 Active-high SPI clock (idles low)
1 Active-low SPI clock (idles high)
Clock Phase — This bit selects one of two clock formats for different kinds of synchronous serial peripheral
devices. Refer to Section 12.5.1, “SPI Clock Formats” for more details.
0 First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer
1 First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPIC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in Table 12-2.
LSB First (Shifter Direction)
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
MODFEN
0
0
1
1
SSOE
0
1
0
1
Table 12-2. SS Pin Function
Master Mode
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
Slave Mode
Slave select input
Slave select input
Slave select input
Slave select input
12.4.2 SPI Control Register 2 (SPIC2)
This read/write register is used to control optional features of the SPI system. Bits 7, 6, 5, and 2 are not
implemented and always read 0.
7
6
5
4
3
2
R
0
0
0
0
MODFEN BIDIROE
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-7. SPI Control Register 2 (SPIC2)
1
SPISWAI
0
0
SPC0
0
MC9S08GT16A/GT8A Data Sheet, Rev. 1
194
Freescale Semiconductor